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mic4720 3mm x 3mm 2.0mhz 2a integrated s w itch buck regulator mlf and mi c r o l eadfram e are re gistered tradema r ks of amkor tec hnolog y , inc. micrel inc. ? 2180 fortu ne drive ? san jose, ca 95131 ? usa ? tel +1 ( 40 8 ) 944 -08 00 ? fax + 1 (408) 474-1000 ? htt p :/ /www.micrel.com may 2007 m999 9-05 170 7 general description the micrel m i c472 0 is a h i gh efficien cy pwm buck (step- down) re gula t or that provides up to 2a of o u tput cu rre nt. the mic4 72 0 operates at 2.0mhz a nd ha s pro p r ietary internal comp ensation th at allows a clo s ed lo op ban d w idth of over 200k hz. the lo w o n -resi stan ce int e rnal p-ch an nel mosfet of the mic472 0 all o ws efficie n ci es over 92% , redu ce s external comp one nts count an d eliminates the need for an expen sive cu rre nt sen s e resi stor. the mi c47 2 0 op erate s from 2.7v to 5.5v input a nd the output ca n b e adju s ted d o wn to 1v. the devices can operate with a maximum d u ty cy cle of 1 00% for use i n low- drop out co ndi tions. the mic4 72 0 is availabl e in the exposed pad 12-pi n 3mm x 3mm mlf ? and 10 -pin epa d msop packa ge with a junctio n ope rating ran ge from ?40 c to +12 5 c . fe ature s ? 2.7 to 5.5v supply voltage ? 2.0mhz pwm mode ? output c u rrent to 2a ? u p to 94% effic i enc y ? 100% maxim u m duty cycle ? adjusta b le ou tput voltage option do wn to 1v ? u l tra-fas t trans ient response ? ultra - small ex ternal comp o nents stable with a 1h ind u cto r and a 4.7f output cap a cit o r ? fully integrat ed 2a mosf et switch ? micropo we r shutdo wn ? thermal shut down and cu rrent limit prot ection ? pb-fre e 12-pi n 3mm x 3mm mlf ? package ? ?40 c to + 125 c ju nctio n tempe r atu r e range ? pb-fre e 10-pi n epad mso p packag e applicati o ns ? fpga/dsp/asic appli c ati ons ? gene ral p o int of load ? broad ban d communi catio n s ? dvd/ tv re co rde r ? point of sale ? printers /sc anners ? set top boxes ? com puting p e rip herals ? video card s ty pical a pplic ation mic4720 65 70 75 80 85 90 95 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 ef fi c i en cy (%) output c urrent (a) mic4720 3. 3v ou t eff i ci enc y v in = 5. 5v v in = 4 . 5v v in = 5. 0v 2 a 2.0mhz bu ck reg u l ato r
mic r el, inc . mic47 2 0 may 2007 2 m999 9-05 170 7 ordering information part nu mb er vo ltag e ju n c tio n t e mp . ran g e pack ag e l ead f i nish mic472 0yml adj. ?40 to + 125 c 12-pin 3 x 3 ml f ? pb-free mic472 0ymme adj. ?40 to + 125 c 10-pin epad msop pb-free pin c onfi gur ation bias en sw vin pgnd sgnd sw vin pgnd pgood 5 1 2 3 4 8 fb nc 67 12 11 10 9 ep 12-pin 3mm x 3mm ml f ? (m l) fb en 6 5 1 sw vin sgnd bias 10 sw vin pgnd pgood 9 8 7 2 3 4 10-pin epad mso p (mm)
micrel, inc. mic4720 may 2007 3 m9999-051707 pin description pin number mlf ? pin number msop pin name pin function 1,12 1, 10 sw switch (output): internal power p-channel mosfet output switch 2,11 2, 9 vin supply voltage (input): supply voltage for the source of the internal p-channel mosfet and driver. requires bypass capacitor to gnd. 3,10 8 pgnd power ground. provides the ground return path for the high-side drive current. 4 3 sgnd signal (analog) ground. provides return path for control circuitry and internal reference. 5 4 bias internal circuit bias supply. must be bypassed with a 0.1f ceramic capacitor to sgnd. 6 5 fb feedback. input to the error amplifier, c onnect to the external resistor divider network to set the output voltage. 7 ? nc no connect. not internally connected to die. this pin can be tied to any other pin if desired. 8 6 en enable (input). logic level low, will s hutdown the device, reducing the current draw to less than 5a. 9 7 pgood power good. open drain output that is pulled to ground when the output voltage is within +/- 7.5% of the set regulation voltage ep ? gnd connect to ground.
micrel, inc. mic4720 may 2007 4 m9999-051707 absolute maximum ratings (1) supply voltage (v in ) .......................................................+6v output switch voltage (v sw ). .........................................+6v output switch current ( sw ).............................................11a logic input voltage (v en ) .................................. ?0.3v to v in storage temperature (t s ) .........................?60c to +150c operating ratings (2) supply voltage (v in ) ..................................... +2.7v to +5.5v logic input voltage (v en ) ....................................... 0v to v in junction temperature (t j ) ........................ ?40c to +125c junction thermal resistance 3mm3mm mlf-12 ( ja ) ...................................60c/w 3mm3mm mlf-12 ( jc )...................................10c/w 10 pin epad msop ( ja )....................................76c/w 10 pin epad msop ( jc )....................................28c/w electrical characteristics (3) v in = v en = 3.6v; l = 1h; c out = 4.7f; t a = 25c, unless noted. bold values indicate ?40c < t j < +125c. parameter condition min typ max units supply voltage range 2.7 5.5 v under-voltage lockout threshold (turn-on) 2.45 2.55 2.65 v uvlo hysteresis 100 mv quiescent current v fb = 0.9 v nom (not switching) 570 900 a shutdown current v en = 0v 2 10 a [adjustable] feedback voltage r 2% (over temperature) i load = 100ma 0.98 1.02 v fb pin input current 1 na current limit v fb = 0.9 v nom 3.5 5 a output voltage line regulation v out > 2v; v in = v out +500mv to 5.5v; i load = 100ma v out < 2v; v in = 2.7v to 5.5v; i load = 100ma 0.07 % output voltage load regulation 20ma < i load < 2a 0.2 % maximum duty cycle v fb d 0.4v 100 % switch on-resistance i sw = 200ma v fb = gnd (high side switch) 95 200 300 m ? oscillator frequency 1.8 2.0 2.2 mhz enable threshold 0.5 0.85 1.3 v enable hysteresis 50 mv enable input current 0.1 2.3 a power good range 7 10 % power good resistance i pgood = 500a 150 250 ? over-temperature shutdown 160 q c over-temperature hysteresis 25 q c notes : 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. specification for packaged product only.
mic r el, inc . mic47 2 0 may 2007 5 m999 9-05 170 7 ty pical characteri stics 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rr en t (a ) m i c 472 0 1. 8v out ef f i ci en cy v in = 3. 0v v in = 3. 3v v in = 3. 6v 65 70 75 80 85 90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rr en t (a ) m i c 472 0 1. 8v out ef f i ci en cy v in = 4. 5v v in = 5. 0v v in = 5. 5v 65 70 75 80 85 90 95 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rre nt (a ) m i c 472 0 2. 5 v out ef f i cie n cy v in = 4. 5v v in = 5. 0v v in = 5. 5v 70 75 80 85 90 95 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rre nt (a ) m i c 472 0 2. 5 v out ef f i cie n cy v in = 3. 3v v in = 3. 6v 65 70 75 80 85 90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rre nt (a ) m i c 472 0 1. 5 v out ef f i cie n cy v in = 3. 0v v in = 3. 3v v in = 3. 6v 65 67 69 71 73 75 77 79 81 83 85 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rre nt (a ) m i c 472 0 1. 5 v out ef f i cie n cy v in = 4. 5v v in = 5. 0v v in = 5. 5v 65 70 75 80 85 90 95 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rr en t (a ) m i c 472 0 3. 3 v out ef f i cie n cy v in = 5. 5v v in = 4. 5v v in = 5. 0v 30 35 40 45 50 55 60 65 70 75 80 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rre nt (a ) m i c 472 0 1v out e f f i c i en cy v in = 5. 0v v in = 4. 5v v in = 5. 5v 50 55 60 65 70 75 80 85 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rre nt (a ) m i c 472 0 1v out ef f i cie n cy v in = 3. 0v v in = 3. 3v v in = 3. 6v 65 67 69 71 73 75 77 79 81 83 85 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rre nt (a ) m i c 472 0 1. 2v out ef f i ci en cy v in =3 .0 v v in =3 .3 v v in =3 .6 v 60 62 64 66 68 70 72 74 76 78 80 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 effi ci enc y ( % ) outp ut cu rre nt (a ) m i c 472 0 1. 2v out ef f i ci en cy v in = 4. 5v v in = 5. 0v v in = 5. 5v 0.9990 0.9992 0.9994 0.9996 0.9998 1.0000 1.0002 1.0004 1.0006 1.0008 1.0010 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) line r e gulation
mic r el, inc . mic47 2 0 may 2007 6 m999 9-05 170 7 ty pical characteri stics (cont.) 0.990 0.992 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 20 40 60 80 temperature (c) feedback vol t age vs. tempera t ure 0.994 v in = 3.3v 1.5 1.6 1.7 1.8 2.0 2.1 2.2 2.3 2.4 2.5 20 40 60 80 temperature (c) fr equ e ncy v s . te mperat ure v in = 3.3v 1.9 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1234 5 supply voltage (v) feedback volt age vs . supply v o lt age v en = v in 0 100 200 300 400 500 600 700 800 0123456 supply voltage (v) q u ie sc ent c u rrent vs. supp ly voltage v en = v in 70 75 80 85 90 95 100 105 110 115 120 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) r ds on vs . s u pply v o lt age 0 20 40 60 100 120 140 160 20 40 60 80 temperature (c) r ds o n vs. temper ature v in = 3.3v 80 0 0.2 0.4 0.6 0.8 1.0 1.2 2.7 supply voltage (v) en abl e thresho ld vs. s uppl y vol t age 3.7 3.2 4.2 4.7 0 0.2 0.4 0.6 0.8 1.2 enable thr eshold v s . te mperat ure 20 40 60 80 temperature (c) v in = 3.3v 1.0
mic r el, inc . mic47 2 0 may 2007 7 m999 9-05 170 7 functi onal characteristics continuous current in du c t or c u r r e nt (5 0 0 ma / d iv ) s w it ch v o lt a g e (2v/d i v) t i me (2 00 ns/div ) v in = 3.3v v out = 1v l = 1h c out = 4.7f i out = 1.3a load t ransien t o u t put current (1 a / d i v ) outp ut v o lta g e (20mv/ di v) t i me (10 0 s /d i v ) v in = 3.3v v out = 1.0v output ripple a c coupl ed (10mv/di v ) sw itc h v o l t age (2v/di v ) o u tput cur r ent (2 a / d i v) t i me (200ns /di v ) i out = 2a o u tput v o l t a g e v in = 3.3v v out = 1.0v
mic r el, inc . mic47 2 0 may 2007 8 m999 9-05 170 7 functi onal dia g ra m vin vin bias en sw sw fb pgood pgnd enable and control logic pwm control p-channel current limit sgnd 1.0v 1.0v soft start bias, uvlo, thermal shutdown hsd ea mic472 0 blo ck diag ram
mic r el, inc . mic47 2 0 may 2007 9 m999 9-05 170 7 pin d e s c r i ption vin two pin s for vin provide powe r to the sou r ce of the internal p-ch annel mosf et alon g with the cu rrent limiting se nsi ng. the vi n operating volt age rang e i s from 2.7v to 5.5v. due to the h i gh switchi n g spee ds, a 1 0 f cap a cito r is recom m en ded clo s e to vin and the p o w er grou nd (pg n d) for e a ch p i n for bypassi ng. please re fer to layout reco mmend ation s . bi as the bia s (bias) provide s p o we r to the internal refere n c e and co ntrol se ction s of t he mic472 0. a 10 ? r e si st o r from vin to bias and a 0.1f from b i as to sgnd is requi re d for cl ean op eratio n . en the en able pin provides a l ogic lev e l cont rol of the output. in the off state, suppl y cu rrent of the device is greatly red u ced (typically <1 a). do n o t drive the enable pin above the supply voltag e. fb the feed ba ck pin (fb) provide s the control pat h to c o n t ro l th e ou tp u t. f o r ad ju s t ab le vers io ns , a r e s i s t o r divider con n e c ting the fe e dba ck to th e output is use d to adju s t the de sire d outp u t voltage. the output voltag e is cal c ulate d as follows: ? 1 ? u 1 r2 r1 v v ref out whe r e v ref is equal to 1.0 v . a feedfor wa rd cap a cito r is r e comm ende d for most desi gn s usi n g the adju s ta bl e output vo ltage option. to redu ce cu rr ent dra w , a 10k feed back re si sto r is recomme nde d from the ou tput to the fb pin (r1). al so, a feedfor w a r d capa citor sho u l d be conn ect ed bet wee n the output and f eedb ack (a cr oss r1 ). th e large r e si stor value a n d th e pa ra sitic capa citan c e o f the fb pin ca n cau s e a hig h frequ ency p o le that can r e du ce the overall system p h a s e ma rgin. by placin g a feedfo r wa rd cap a cit o r, t hese ef f e ct s can be signi f i cant ly redu ced. f e e d f or wa r d c a pa c i ta nc e ( c ff ) can be calcul ate d a s follows : 200khz r1 2 1 c ff u u s sw the switch ( s w) pin co n nect s dir e ctly to the indu ctor and p r ovide s the switchi n g cur r e n t ne ce ssary to op er ate in pwm mod e . due to the high spe e d swit chin g on this pin, the swi t ch nod e sh ould be r o u t ed away fr om s e ns itive no de s . t h is p i n als o c o n n ec ts to th e c a th ode o f the free- wh ee ling diode. pgoo d powe r g ood is a n o p en d r ain pull do wn that i n dicates whe n the out put voltage h a s r e a c he d r egulatio n. fo r a power go od low, the outpu t voltage is within 10% of the set re gulatio n voltage. f o r outp ut voltages gre a te r or less than 1 0 % , the pgood pin i s hig h . this shoul d be c o nnec ted to the input s u pply throu g h a pull u p re si stor. a delay can be added by placing a capa citor fr om pgoo d to gr ound. pgnd powe r gro u n d (pgnd) i s the gro u n d path for the mosfet dri v e cur r ent. t h e cu rr ent lo op for the po wer grou nd sh oul d be a s sm all a s p o ssib le an d sepa r a te from the sig n a l gr ound (s gnd) loop. refer to the layout c o ns iderations for more details . sgnd signal g r ou n d (sg n d) i s t he g r ou nd p a t h for the bia s ing and control cir c uitry. the cur r ent loo p for the si gnal grou nd sho u l d be sep a r a te from th e po we r g r o und (pgnd ) loop. r e fer to the layo ut consi d eration s fo r m o re details .
mic r el, inc . mic47 2 0 may 2007 10 m999 9-05 170 7 applicati on inf o rm ation the mi c47 2 0 is a 2a pwm n on- sy nch r on ou s b u ck r e g u la to r . by sw itc h in g an in pu t vo ltag e s u pp ly, an d filtering the swit che d voltage th rou g h an ind u cto r and cap a cito r, a r egulate d dc voltage i s o b t ained. fi gur e 1 sho w s a sim p lified examp l e of a no n- synchr o no us b u ck conve r ter. figur e 1 . ex a m ple of n on-s y n c h r onous buc k c o n v er ter for a non -sy n ch ron o u s b u ck conve r te r, there are two mode s of o peratio n; co nt inuou s a n d disco n tinu ous. contin uou s or di scontin uou s refe r to the indu ctor cur r e n t. if curre nt is conti nuou sly flowi ng throu gh the indu ctor th r ough out the swit chin g cycle, it is in contin uou s o peratio n. if the indu ctor cur r e n t drop s to zer o du ring t he off time, it is in di sconti nuou s op er ation. critically co ntinuou s is th e point wh er e any decre ase in output current will cause it to enter discontinuous oper ation. th e criti c ally co ntinuou s loa d cur r ent can be cal c ulate d as follows; l 2 2.0mhz v v v i in 2 out out out ? ? ? ? ? ? ? ? ? = contin uou s o r di scontinu o u s o p e r ation determi ne s h o w we calculate pea k indu ctor cur r ent. con t inuous opera t ion figure 2 illustrates the swit ch volt age and inductor cur r e n t durin g contin uou s oper ation. figur e 2 . con t inu ous o p e r a tion the o u tput voltage is reg u lated by pulse width modulatin g ( p wm) the switch voltage to the average requi re d outp u t voltage. the swit ching can be bro k e n up into two cycl e s ; on and off . during th e on-time, the high sid e swi t ch is turn ed on, cur r e n t flows from the in p u t sup p ly thr ough th e ind u ctor and to the out put. the indu ctor cur r ent i s figur e 3 . on- time cha r ge d at the rate; ( ) l v v out in ? to dete r min e the total o n -time, or ti me at whi c h the indu ctor cha r ges, the duty cy cle ne ed s to be cal c ulat ed. the duty cycl e can b e cal c ulated a s ; in out v v d = and the on ti me is; 2.0mhz d t on = ther efore, pe ak to pea k rip p le cu rr ent is; () l 2.0mhz v v v v i in out out in pk pk ? = ? since the averag e pe ak t o pea k cur r e n t is eq ual to the load cu rre nt. the a c tual pea k ( o r hi g hest cu rre nt the inductor will see in a steady state condition) is equal to the output cu r r ent plu s ? the pea k-to -pe a k cur r ent. () l 2.0mhz 2 v v v v i i in out out in out pk ? + = figur e 4 dem onstr ates the off-time. dur i ng the off-time, the high-s i de internal p-c h annel mosfet turns off. since the cu rre nt in the indu ctor ha s to discha rge, the
mic r el, inc . mic47 2 0 may 2007 11 m999 9-05 170 7 cur r e n t flows throug h the free- whe e lin g schottky di ode to the outp u t. in this ca se, the ind u cto r discha rge rat e is (wh e r e v d is the diod e forward voltage ); () l v v d out + ? the total off ti me c an be c a lc ulated as ; 2.0mhz d 1 t off ? = figur e 4 . off- time discon t inuo us oper atio n disco n tinuou s ope ration i s wh en the indu ctor cur r ent discha rge s to zer o duri ng the off cycle. figu r e 5 demon str a tes the switch voltage a nd i ndu ctor cu rr e n ts durin g disco n t inuou s ope ra tion. f i g u re 5. disco n t in uo u s op eratio n w h en th e in d u c t o r c u rr en t ( i l ) ha s com p let e ly discha rge d , the voltage o n the switch node ring s at the freque ncy d e t ermine d by the pa ra sitic cap a cita nce and the indu ctor value. in fig u re 5, it is dra w n a s a dc voltage, but t o see a c tual oper at ion (wit h rin g ing ) ref e r to the function al char acte ri stics. disco n tinuou s mo de of oper ation h a s the advant age over full pwm in that at li ght loads, the mic4720 will ski p pulses as nessa sa ry, r edu cing gat e drive lo sse s , dra s tically im proving lig ht load efficie n cy . efficiency considera t ion s cal c ulating t he efficien cy is as sim p l e as mea s u r ing power out an d dividing it by the power i n ; 100 p p efficiency in out = whe r e inp u t power (p in ) is; in in in i v p = and outp u t po wer (p out ) is cal c ulate d as; out out out i v p = the efficie n cy of the mi c4720 is dete r mined by several f a ct or s. ? rd son (inte r n a l p-ch ann el re sista n ce) ? diod e co ndu ction losse s ? inducto r co n ductio n losse s ? switching losses rd son lo sse s are cau s ed by the cu rre n t flowing thro ugh the hig h side p-ch ann el m o sfet. the amount of p o w er loss ca n be a pproxim ated by; d i r p 2 out dson sw = whe r e d i s th e duty cycle. since the mic472 0 u s e s an internal p-ch a nnel mosfet, rdso n lo sses are i n versel y prop ortion al to sup p ly voltag e. hig her su pply voltage yields a hi g her gate to sou r ce voltage, red u ci n g the rd son, re du cing t h e mosfet co ndu ction lo sses. a gra p h sho w ing typ ical rd son vs i n p u t su pply volt age ca n b e fo und i n the typical cha r a c teri stics se ction of this data s h eet . diod e cond u c tion lo sse s occu r du e to the forward voltage d r op (v f ) and th e outp u t current. dio de p o we r losse s ca n be approxim ate d as follo ws; ( ) d 1 i v p out f d ? = for thi s rea s on, the sch o ttky diode i s the re ctifier of choi ce. using the lowest fo rward voltage drop will hel p redu ce di ode con d u c tion lo sses, an d improve efficie n c y. duty cycle, or the ratio of output voltage to input voltage,
mic r el, inc . mic47 2 0 may 2007 12 m999 9-05 170 7 determi ne s wheth e r the domina n t factor in con d u c tion losses will be the internal mosfet or the schottky diode. high er duty cycle s plac e the p o w er losse s o n the high side swi t ch, and l o we r duty cycl es place the po we r loss es on the sc hottk y diode. inducto r con ductio n lo sse s (p l ) can b e calculated by multiplying th e dc re sista n ce (dcr) times th e squ a r e of the output cu rrent; 2 out l i dcr p = f i g u re 6. s w itch in g t ran sitio n lo sses normally, wh en the switch is on, the vo ltage acro ss the swit ch i s low (virtually ze ro ) and th e cu rrent through t h e swit ch i s hi g h . this eq ua tes to lo w p o we r di ssipat ion. when the swi t ch is off, voltage across the switch i s hi gh and the cu rrent is ze ro, again with p o we r di ssipat ion being lo w. during the tra n s ition s , the voltage acro ss the swit ch (v s-d ) and th e cu rre nt thro ugh th e switch (i s-d ) ar e at middle, causi ng the tr an sition to be the high est instanta neo u s po we r poi nt. durin g continuo us m ode, these lo sse s are the hig hest. also, with high er l oad curre n ts, the s e l o sse s are hig her. fo r di scontinu o u s operation, the tran sition l o sse s o n ly occu r du rin g the ?off? transitio n sin c e the ?o n? t r an sition s there is n o cu rrent flow throu gh the indu ctor. also, be a w are th at the r e are a dditio nal core lo sse s asso ciated with swit chin g curre n t in an indu ctor. si nce most i ndu cto r ma nufa c turers d o n o t g i ve data on the type of material used, approxim ating co re lo sse s becomes very diffic u lt, s o verify inductor temperature rise. switchin g lo sses o c cur twice ea ch cycle, wh en the swit ch turns on and when the switch turns off. this is cau s e d by a non-i deal world where swit chin g tra n siti ons are n o t instan taneou s, and neit her are currents. fig u re 6 demon strates ho w swit chin g lo sse s d ue to the transitio ns di ssipate p o wer in the swit ch.
mic r el, inc . mic47 2 0 may 2007 13 m999 9-05 170 7 component sel ecti on diode selec t ion since the mi c47 20 is non -syn ch ron o u s, a free-whe e ling diode is requi red for prope r o peration. a schottky di ode is re co mmen ded du e to the low fo rwa r d voltage drop and their fa st reverse re covery time. the diode sho u ld be rated to b e able to han dl e the avera ge output current. also, the re verse voltag e rating of the diod e sh oul d excee d the maximum in put voltage. the lo we r the forwa r d volt age d r op o f the diode the better the effic i enc y. please refer to t he layout re commen dation s to minimize switchin g noi se. input ca paci tor a 10f ce ra mic is re com m ende d on each vin pin for bypassin g . x5r o r x7 r diele c trics a r e recomme n ded for the input c a pac i tor. y5v di elect r ics l o se most of their cap a cita nce over tem perature and a r e the r efo r e not recomme nde d. also, tantal um an d el ectrolytic capa cit o rs alone a r e n o t recomme n ded d ue thei r re du ced rms current handli ng, reliability, and esr increases. an additio nal 0.1f i s recommen ded close to the vin and pg nd pi ns for high freque ncy filtering. smaller case size capa cito rs are reco mmend ed d ue to thei r l o we r esr and esl. please refer to layout recom m en dati ons for pro per lay out of the input capa citor. feedb ack resistor s the fee dba ck resi sto r set the outp u t voltage by dividing down the out put and sendi ng it to the fe edba ck pin. t h e feedba ck vol t age is 1.0v . calculating the set o u tput voltage is a s follows; outpu t c a pa citor the mic472 0 is de sig n e d fo r a 4.7f output ca pa citor. x5r or x7 r diele c trics a r e recomme n ded for the o u tput cap a cit o r. y5v dielect r i cs l o se mo st of their capa cita nce over tempe r a t ure and a r e t herefo r e n o t recom m en ded . ? ? ? ? ? ? + = 1 r2 r1 v v fb out whe r e r1 i s t he re sisto r from vo ut to fb and r2 i s the resi sto r fro m fb to g n d. the re com m ende d fee d back resi sto r value s for commo n output voltag es are availa ble in the bill of material s on page 19. although the range of resi st an ce f o r t h e fb r e sist o r s is v e ry wid e , r 1 is recomme nde d to b e 1 0 k. thi s minimizes the effec t the para s itic cap a citan c e of th e fb node. in addition to a 4.7f, a small 0.1f i s recomme n ded clo s e to the load fo r hig h freq uen cy filtering. sma ller ca se si ze ca pacito r s a r e recomme nde d due to there lowe r equival ent seri es es r and esl. the mic4720 utilizes type iii voltag e mode internal comp en satio n an d utili ze s a n int e rnal zero to comp en sate for the dou ble pole roll of f of the l c fi lter. for thi s rea s on, l a rg er out put cap a citors ca n create instabilities. in ca ses where a 4.7f output capacitor is not sufficient, the mic472 0 offers the ab ility to extern ally control the compen satio n , allowing fo r a wide rang e of output ca pa ci tor types and values. feed for w a r d capaci tor (c ff ) a cap a cito r across th e resi stor f r om the outp u t to the feedba ck pin (r1) i s re commen ded f o r mo st d e si gns. this ca pa cito r can give a boo st to ph ase ma rgin and increa se the band width f o r tra n si ent respon se. al so, large value s of feedfo r wa rd capa citan c e can slo w d o wn the turn -on chara c te risti c s, redu cing i n rush cu rrent. for maximum ph ase b o o s t, c ff can be calculated a s follows; inductor sel ection the mic472 0 is d e si gne d for u s e with a 1 h indu ctor. prope r sele ction shoul d e n su re th e ind u ctor can h a ndle the maximum avera ge a n d pea k current s requi red by the load. m a ximum curre n t rati ng s of the in du ctor are gene rally giv en in two me t hods; p e rmi s sible dc cu rrent and satu ratio n current. pe rmissibl e dc cu rrent can be rated eith er f o r a 40 c te mperature rise or a 1 0 % to 20% loss in ind u ctance. en su re the indu ct or sele cted can handl e the m a ximum op erating current. whe n satura tion curre n t is sp ecified, m a ke su re th at there i s e n o ugh margi n that the peak current will not saturate the indu ctor. r1 200khz 2 1 c ff = bias filte r a small 10 resi stor is recom m en ded from the input sup p ly to the bias pi n alo ng with a sm all 0.1f cerami c cap a cito r fro m bias to g r o und. thi s will bypass the high freque ncy no ise gen erate d by the violent swit ching of high cu rrents from re achi ng the inte rn al refere nce and control ci rcuitry. tantalum and ele c trolytic ca pa citors are not recomme nded for the bias, th ese ty pes of ca pa ci tors lose thei r abili ty to filter at high frequ en ci es.
mic r el, inc . mic47 2 0 may 2007 14 m999 9-05 170 7 loop stability and bode analy s is bode analysi s i s an excellent way t o me asure small sign al stabili ty and l oop re sp on se i n po we r su pply desi g n s . bod e an alysis m onitors g a in and pha se o f a control lo op. this i s d one by bre a ki ng t he feed ba ck l oop and i n je cting a sign al in to the fe ed back nod e and comp ari ng th e inje cted sig nal to the o u tput sig nal of the control loop. this will requi re a net work analyzer to sweep th e fre quen cy an d compa r e the i n jecte d si gna l to the outp u t si g nal. the mo st comm on m e thod of inje ction is the u s e of transfo rme r . figure 7 dem onstrates ho w a transfo rme r i s used to inj e ct a sig nal into the feedb ack netwo rk. f i g u re 7. t ran sfo r mer in jectio n a 50 ? re sist or all o ws im peda nce mat c hin g from the netwo rk a nal yzer source. thi s m e tho d allo ws the dc loop to mai n tain re gulat ion and allo w the net work analyzer to i n sert an a c si gnal o n top o f the dc volta ge. the network analyzer will then sweep t he source while monitori ng a and r for a n a/r mea s ure m ent. while t h is is the m o st common meth od for m e a s u r ing the gain and pha se of a powe r sup p ly, it does have sig n ificant limitations. fi rst, to mea s ure lo w fre q uen cy gain and pha se, the transfo rme r ne eds to be hig h in indu ctan ce. this makes freque nci e s <10 0 hz req u i re a n extre m ely large and ex pen sive tran sformer. conv ersely, it must be able to inje ct high freq uen cie s . tran sfo r mers with th ese wide frequ en cy ran g e s g enerally nee d to be cu stom made an d are extremely expen sive (u sually in the tune of several hu ndre d dolla rs!). by using an op -amp, co st and frequ e n cy limitatio ns use d b y an inje ction transfo rme r are co m p letely elimi nated. fig u r e 8 demon strates using a n op -amp in a su mming amplif ier config uratio n for sign al inje ction. n e t w or k a na l y z e r source +8 v r1 1k r3 1k r4 1k 50 f e ed ba c k o u t put ne t w o r k analyzer ?a? input ne t w o r k analyzer ?r? input mi c 9 2 2 b c 5 figur e 8 . op a m p inje c t ion r1 and r2 re duce the dc volt age from the output to the non-i n verting input by h a lf. the net work a nalyzer i s gene rally a 5 0 ? sou r ce. r1 an d r2 also divide the ac sign al sou r ce d by th e n e twork an alyze r by half. th ese two sign als are ?summ e d? to gethe r at half of their origin al input. the outp u t is then g a ine d up by 2 by r3 and r4 (th e 50 ? i s to ba lance the net work a nalyze r?s sou r ce imp e d ance) a nd se nt to the feed back sign al. this essentially b r eaks the l oop and inje cts t he ac sign al on top of the dc output v o lt age a nd sen d s it to the feedba ck. by monitorin g the feedb ack ?r? and out put ?a?, gain and pha se a r e m easure d . thi s method h a s no minimum fre quen cy. en sure that the band width of the op-a m p bei n g use d is m u ch g r eate r th an the expe cted band width of the po we r su pplie s control loop. an op -amp with >10 0 m h z band width i s more tha n sufficient for most power sup p lies (whi ch inclu d e s both line a r and swit chin g) a nd are m o re comm on and si gnifica ntly che ape r tha n the inje ct ion tra n sfo r mers p r evio usly mentione d. the one di sa d v antage to u s ing the op-a m p injectio n method; is the supply voltage s nee d to be low the maximum ope rating vol t age of th e o p -am p . also, the maximum o u tput voltage fo r drivin g 5 0 ? inputs usi ng t h e mic922 i s 3 v . for mea s uring highe r output voltag es, 1m ? inp u t impeda nce is requi red fo r the a and r cha nnel s. rememb er to always m e asu r e th e o u tput voltage with an oscilloscope to ensure the measurement is working properly. you should see a singl e swee p i ng sinu soi dal waveform with out disto r tion on the outp u t. if there is di sto r tion of the si nusoid, red u ce the amplitu de of the so urce sig nal. yo u co uld b e overd r iving t h e feedba ck ca u s ing a la rge signal re sp on se.
mic r el, inc . mic47 2 0 may 2007 15 m999 9-05 170 7 the follo wing bode an alysis show th e small sig nal lo op s t ability of the mic4720, it utiliz es type iii c o mpensation. this i s a do minant lo w freque ncy p o l e , followe d b y 2 zeros an d f i nally the d ouble pole of the in du ctor cap a cito r filter, creatin g a final 20 db/deca de roll off. bode a nalysi s give s us a few impo rt ant data poi nts; spe ed of respon se (g ain bandwi d th o r gbw) and l oop s t ability. loop s p eed or gb w determines the res p onse time to a load tran sient. fa ster re sp onse times yield smalle r volta ge deviation s to load step s. instability in a control loo p occurs when there is gai n and positive fe ed back. ph ase margi n i s the mea s u r e of how stable the giv en system i s . it is mea s u r e d by dete r min i ng how fa r the p hase is from cro s sing ze ro whe n the g a i n is equal to 1 (0 d b ). typically for 3.3vin and 1. 8vout at 2a; ? phase margi n =47 degr ee s ? gbw=156 khz gain will al so increase with input voltage. the foll owing grap h sho w s the in cre a se in gb w fo r an incre a se in sup p ly voltage. 5vin, 1.8vout at 2a load; ? phase margi n =43. 1 degr ees ? g b w = 21 8kh z being that the mic4 72 0 is non -sy n ch ron o u s ; the regul ator onl y has the ability to source current. this mean s that t he regul ator has to rely o n the l oad to be able to sin k curre n t. this cau s e s a no n-line a r resp onse at light load s. the follo win g plot shows the effects of the pole cre a ted by the non linear ity of the output d r ive durin g light lo ad (di s contin uou s) conditi ons. 3.3vin, 1.8vout iout=50ma ; ? phase margi n =90. 5 degr ees ? gbw = 64.4kh z feed for w a r d capa citor the feed ba ck resi sto r s are a gain red u ction blo ck i n th e overall syste m re sp on se of the regul a t or. by pla c in g a cap a cito r fro m the outpu t to the feedba ck pin, h i gh freque ncy si g nal can byp a ss the resi sto r divider, ca u s ing a gain in cre a s e up to unity gain. -1 0 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 gain ( d b) fr eq uency ( h z) gain an d phas e vs. fre q u e ncy 0 5 10 15 20 25 phas e boost ( ) 10 0 1 k 10 k 100 k 1m l= 1 h c ou t = 4.7 f r1 = 1 0 k r 2 = 12 .4k c ff = 82 pf gain p h ase the g r ap h a bove sho w s the effects o n the gai n a n d pha se of th e system ca use d by feed ba ck resi sto r s an d a feedforwa rd cap a cito r. th e maximum amount of p hase boo st achie v able with a f eedfo r wa rd capa cito r is grap hed b e lo w.
mic r el, inc . mic47 2 0 may 2007 16 m999 9-05 170 7 0 5 10 15 20 25 30 35 40 45 50 12345 pa hs e bo o s t ( ) ou tput vol t a g e ( v ) m ax. amount of p h ase boost obtaina b le using c ff v s . output vo l t ag e v ref = 1v as you can see th e typical p h a s e m a rgin, u s in g the same re si sto r value s a s before with o u t a feedfo r ward cap a cito r re sults in 33.6 d egre e s of p h a se ma rgin. our prio r mea s u r ement with a feedforward cap a cito r yielded a pha se m a rgin of 47 degre e s. the feedfo r ward cap a cito r ha s given us a pha se boo st of 13.4 degree s (47 de gree s- 33.6 de gre e s = 13.4 de gre e s). by looking at the grap h, ph as e ma rgin can be affecte d to a greate r de g r ee with hi gh er output voltage s. the next bo d e plot sh ows the p h a s e margi n of a 1.8v output at 2a without a fe e d forward ca p a citor.
mic r el, inc . mic47 2 0 may 2007 17 m999 9-05 170 7 out put im pe da nc e and tra n sient response output imp e dan ce, si mpl y st ated, is the amo unt of output voltag e deviation v s . the load current deviati on. the lower the output imped ance, the better. out out out i v z ? ? = output impe dan ce for a buck regulat or is the p a rallel impeda nce of the output ca pacito r an d th e mosfet a nd indu ctor divid ed by the gai n; cout l dson total x gain x dcr r z + + = to mea s u r e output impe d ance vs. freq uen cy, the load curre n t must be load curre n t must be swept a c ro ss the freque nci e s measured, while the o u tput voltage is monitored. figure 9 sho w s a test set-up to measu r e output impe dan ce fro m 10hz to 1mhz u s ing the mic519 0 hig h spe ed controller. f i g u re 9. o u t p u t imp e d a n c e measu r e me n t by setting up a net work a nalyze r to sweep the f eed bac k curre n t, whil e monito ring the outp u t of the voltag e regul ator a n d the voltag e acro ss th e load resi sta n ce, output impe dan ce is e a s ily obtaina b l e. to kee p the curre n t from being to o hi gh, a dc offset n eed s to b e applie d to the netwo rk anal yzer? s sou r ce sign al. this can be done with an external supply and 50 resi st o r . mak e sure that the currents are ve rified with an oscilloscope first, to en su re the inte grity of the signal measurement . it is al way s a goo d id ea to mo nitor the a an d r measurement s with a sco pe while you are sweepin g it. to co nvert the network analyzer dat a from dbm to somethi ng m o re u s eful (such as pea k to pea k voltage and current in our ca se ); 707 . 0 2 50 1mw 10 v 10 dbm = ? and pe ak to p eak cur r e n t; load 10 dbm r 707 . 0 2 50 1mw 10 i = ? the followi n g grap h sh ows output impedan ce vs freque ncy at 2a load cur r ent swe epin g the ac cur r ent from 10 hz to 10mhz, at 1a peak to pe ak amplitude. 0 . 001 0. 0 1 0. 1 1 o u t p ut i m p e danc e ( o hms) f r eq uenc y (hz) outp ut imp e da nc e vs. fr eq uen c y 100 1k 10 k 100 k 1m v out =1.8 v l=1 h c out =4 .7 f + 0 . 1 5v in 3.3 v in 10 from this g r aph, you can see the effects of ban dwidth and o u tput capa citan c e. for fr equ en ci es <20 0 khz, the output impe dan ce i s d o minated by the gain an d indu ctan ce. for fr equ en cie s >200k hz, the ou tput impeda nce is domin ated by the cap a citan c e. a good appr oximatio n for tra n si en t re spo n se can b e cal c ul ated from dete r mi ning the f r eq uen cy of the l oad step in a m ps per second; 2 a/sec = f then, d e term ine the o u tpu t impedan ce by looki ng at the output imp e d ance vs f r eq uen cy gr aph. then calculating the voltage d e viation times the load step ; out out out z i v ? = ? the output i m peda nce g r aph sho w s the r e lation ship betwe en sup p ly voltage and out put im peda nce. thi s is cau s e d by th e lo we r rd son of the hig h si de mos f et and the i n cre a se i n gai n with incr ea sed sup p ly voltag es. this expl ain s why high er supply volta ges h a ve be tter transi ent re sp onse. cout l dson total x gain x dcr r z + + =
mic r el, inc . mic47 2 0 may 2007 18 m999 9-05 170 7 ripp le measu r emen ts to pr ope rly measur e rip p l e on eithe r in put or o u tput of a swit chin g re g u lator, a p r op er rin g in tip measur ement is requi red. standard oscilloscope probe s com e with a grou ndin g cli p , or a long wire with a n alligator cl ip. unfortu nately , for hi gh f r eque ncy m e asu r em ents, this grou nd clip ca n pi ck-u p high fre q uen cy noi se and erroneously inject it into the measur ed o u tput ripple. the sta nda rd evaluation b oard acco m m odate s a h o me made ver s io n by providing pro be po ints for both the input an d out put su pplie s and thei r r e spective g r o u n d s. this requi res the removing of the oscilloscope probe sheath and ground clip fr om a standard oscilloscope prob e an d wr appin g a n o n - shi e lde d bu s wir e ar oun d the oscilloscope probe. if there does not happe n to be any non shiel ded bus wi re im mediately av ailable, the l ead s from axial resi stors will work. by maintaining the shortest possible ground lengths on the oscilloscope prob e, true ri pple mea s u r e m ents can be obtained.
mic r el, inc . mic47 2 0 may 2007 19 m999 9-05 170 7 re comm ende d la y out: 2a evaluation board re c o mme nded to p la y out re c o mme nded bottom la y out
mic r el, inc . mic47 2 0 may 2007 20 m999 9-05 170 7 mic4720 schemati c and bom for 2a out put i t e m p a r t nu mb e r desc rip t io n man u f actu rer q t y c1a,c1 b c 2 0 1 2jb0j 1 0 6 k g r m219r 60j 106ke 19 080 56d 106ma t 10f cer a mic capac itor x5r 080 5 6.3v 10f cer a mic capac itor x5r 080 5 6.3v 10f cer a mic capac itor x5r 080 5 6.3v td k murata avx 2 c2 040 2z d10 4 ma t 0.1f ceramic capacit or x5r 0402 1 0 v avx 1 c 3 c 2 0 1 2jb0j 4 7 5 k g r m188r 60j 475ke 19 060 36d 475ma t 4.7f ceramic capacit or x5r 0603 6.3 v 4.7f ceramic capacit or x5r 0603 6.3 v 4.7f ceramic capacit or x5r 0603 6.3 v td k murata avx 1 c4 vj040 2a82 0k xaa 82pf cer a mic capac itor 04 02 visha y vt 1 d1 ssa33l 3a schottk y 3 0 v sma visha y sem i 1 rlf 7 0 30-1 r 0 n 6r4 1h ind u ctor 8 . 8m ? 7.1mm(l ) x 6.8mm (w )x 3.2mm(h) t d k 1 744 7 78 9 001 1h ind u ctor 1 2 m ? 7.3mm(l) x7.3mm(w ) x3. 2 mm(h) w u rth elektron ik 1 l1 ihlp25 25ah- 0 1 1 1h ind u ctor 1 7 .5m ? 6.47m m(l)x6.86mm( w ) x1.8mm(h) visha y d ale 1 r 1 , r 4 c r c w 04 021 0 0 2 f 10k ? 1 % 04 02 resistor visha y d ale 1 r2 crcw 04 026 6 51f crcw 04 021 2 42f crcw 04 022 0 02f crcw 04 024 0 22f 6.65k ? 1 % 04 02 f o r 2.5v out 12.4k ? 1 % 04 02 f o r 1.8 v out 20k ? 1% 040 2 f o r 1.5 v out 40.2k ? 1 % 04 02 f o r 1.2 v out o pen f o r 1.0 v out visha y d ale visha y d ale visha y d ale visha y d ale visha y d ale 1 r 3 c r c w 04 021 0 r 0 f 10 ? 1 % 04 02 r e sistor visha y d ale 1 u1 mic472 0bml 2.0mhz 2a buck reg ulator micrel, inc. 1 notes : 1. tdk: www.tdk.com 2. murata: www.mu rata.com 3. avx: www.avx.c o m 4. vishay : www.visha y .com 5. wurth elektronik: www. w e -online.com 6. micrel, inc: www .micr e l.com
mic r el, inc . mic47 2 0 may 2007 21 m999 9-05 170 7 package inform ation 12-pin 3mm x 3mm ml f ? (m l) micrel, inc. 2180 fortune drive san jose, ca 9513 1 usa t e l + 1 (408) 9 44-0 800 f a x + 1 (408) 47 4-1 000 w eb http:/ w w w . m i crel.co m the infor m ation fur n ished b y micrel in this data sh eet is belie ved to be accur a te and r e liable. ho w e ver , no r e sponsibility is a ssumed by micr el for its use. micrel reserves the right to change circuitry a n d specificati ons at an y time w i tho u t notification to the customer. micrel products are not designed or autho r iz ed for use as components in life support ap pliances, devi c es or sy stems where malfu nction of a product r e a s o n a b l y b e expected to res u lt in personal inj u ry . life su ppor t devices or sy stems ar e devices or s y stems that ( a ) ar e in tende d f o r s u r g i c a l i m p l a into the bod y or (b) support o r sustain life, and w h o s e failure to perf orm can be re asonabl y e x pected to result in a significan t injury to th e user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or s y stems is a purchaser?s ow n risk and purchaser agre e s to full y indemnif y micrel for an y damages resulting from such use or sale. c a n n t ? 2006 micrel, in corporated.

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